NPU/AI Processor Synthesis Lead

About Qualcomm

Qualcomm India Private Limited operates within the Engineering Group focusing on cutting-edge hardware engineering projects. The company values innovation and teamwork to deliver advanced semiconductor technology.

Role Summary

The NPU Synthesis Lead will take charge of synthesis and timing closure activities for Neural Processing Unit (NPU) intellectual property and its subsystems embedded in state-of-the-art System on Chips (SoCs). This role demands overseeing synthesis flows, enhancing performance, power efficiency, and area metrics (PPA), while coordinating with architecture, RTL, and physical design teams to create top-quality gate-level netlists optimized for the latest technology nodes.

Key Responsibilities

• Own and manage RTL-to-gate-level synthesis for NPU IP and related subsystems employing industry-standard synthesis tools like Synopsys Design Compiler and Cadence Genus.
• Build, maintain, and improve synthesis scripts and flows supporting both hierarchical and flat design methodologies.
• Lead timing closure efforts before and after layout stages across different voltage and process corners to meet timing requirements.
• Partner with Static Timing Analysis (STA) teams to identify and fix setup and hold timing violations.
• Implement physical-aware synthesis techniques to hit ambitious performance, power, and area targets.
• Apply power reduction strategies using Unified Power Format (UPF) or Common Power Format (CPF) flows to enable low-power designs.
• Ensure accuracy and completeness of Synopsys Design Constraints (SDC) files including clocks, IO delays, multi-cycle paths, and false path specifications.
• Collaborate closely with RTL design, Design for Test (DFT), and physical design teams to ensure seamless design handoffs and quality.
• Communicate improvements and feedback to architecture and RTL teams aimed at enhancing quality of results (QoR).
• Conduct quality assurance checks such as Logical Equivalence Checks (LEC), Clock and Power validations (CLP), along with code linting.
• Explore and introduce advanced synthesis techniques and Electronic Design Automation (EDA) tool enhancements to continually improve synthesis quality and efficiency.
• Lead, mentor, and guide junior engineers, promoting best practices in synthesis and timing closure disciplines across teams.

Qualifications and Experience

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or other related engineering discipline with at least 3 years of experience in Hardware Engineering or equivalent.
• Alternatively, a Master's degree in relevant fields with a minimum of 2 years of practical hardware engineering experience.
• Or PhD holders with 1 or more years of applicable hardware engineering background.

Additional Information

Qualcomm is committed to equal opportunity employment and provides reasonable accommodations for applicants with disabilities during the recruitment process. Qualified individuals seeking accommodations may contact the company through designated channels for support. Employees are expected to uphold all company policies, including securing confidential information. Note that recruitment agencies are not authorized to submit applications on behalf of candidates; unsolicited resumes will not be accepted.