Senior / Staff Layout Engineer (CAD & APR Automation)

Position Overview

We are looking for an experienced Layout Engineer skilled in computer-aided design (CAD) to join our Custom Layout engineering team. This role involves hands-on implementation of APR layouts as well as innovating through automation to enhance workflow efficiency and design methodology.

Key Duties

• Perform complete APR layout cycles using tools like Innovus, ICC2, or Fusion Compiler for Foundation IP, Analog IP, RFIC, and digital blocks.
• Act as the single point of responsibility (DRI) for layout automation flows, encompassing APR implementation, physical verification, and final sign-off.
• Execute floorplanning, power mesh strategy, strategic block placement, and hierarchical layout assembly optimized for power, performance, and area (PPA).
• Deliver centralized CAD layout assistance to various teams including Foundation IP, Analog/RF, and SoC across multiple projects.
• Design, upkeep, and improve automated layout workflows from initial development through to deployment in production.
• Develop scripting tools using Python, Tcl, SKILL, and Perl for automation and workflow streamlining.
• Build scalable CAD infrastructures such as parameterized cells (p-cells), modular templates, and reusable architectures.
• Integrate AI and Agentic AI technologies within layout workflows to enhance productivity.
• Define and promote standardized CAD protocols and best practices across different project implementations.
• Leverage backend layout expertise across planar, FinFET, and GAA process nodes from top foundries.
• Master complex Design Rule Manuals (DRMs), Design for Manufacturability (DFM) needs, and advanced physical verification procedures.
• Carry out comprehensive physical verification (DRC, LVS, ERC, ANT, PERC) with expert troubleshooting skills.
• Ensure layouts meet electrical and reliability standards including EM/IR, signal integrity (SI/PI), and electrostatic discharge (ESD) protection.
• Develop new approaches or enhanced methodologies to uplift team productivity.

Qualifications

• Bachelor's degree in Electrical or Electronic Engineering or a related discipline.
• Over 8 years of experience encompassing APR layout implementation and CAD automation development.
• Strong proficiency in CAD with a history of developing workflows, tools, and scripts that drive productivity gains.
• Hands-on experience with APR tools such as Cadence Innovus, Synopsys ICC2, and/or Fusion Compiler.
• In-depth understanding of CMOS layouts across planar, FinFET, and GAA nodes, including mastering DRM and DFM guidelines.
• Advanced skills in physical verification and debugging using tools like Calibre or PVS.
• Expert scripting capabilities in Python, Tcl, SKILL, and Perl to facilitate tool automation and flow optimization.
• Knowledge of floorplanning, power distribution mesh design, critical routing, and hierarchical layout integration.
• Outstanding communication skills, capable of coordinating multiple concurrent projects across teams.
• Experience or familiarity with applying AI or Agentic AI in electronic design automation workflows is advantageous.
• Additional exposure to Foundation IP (IO/ESD), RF/Analog layout, signal integrity, or EM/IR analysis is favorable.