System Performance Modeling Engineer/Architect

About Bitdeer

Bitdeer is a leading global technology company specializing in Bitcoin mining and AI cloud services. With headquarters in Singapore and operations worldwide, including the US, Bhutan, Norway, Canada, Malaysia, and Ethiopia, Bitdeer manages a diversified 3 GW energy portfolio deploying Bitcoin mining and HPC datacenters. The company offers comprehensive solutions across the Bitcoin mining value chain, from ASIC chip design and mining rig manufacturing to equipment procurement, logistics, data center design and operation, as well as advanced AI cloud solutions.

Role Overview

The role involves creating predictive models to estimate chip performance before RTL development, continually refining these as designs evolve. Responsibilities encompass modeling the full chip including the EtHash tile array, proprietary Network-on-Chip (NoC), and 3D-DRAM bandwidth pathways, which influence key architectural decisions such as tile count, local memory size, NoC bandwidth, and memory QoS to meet performance goals within power and thermal constraints. The engineer acts as the quantitative adviser to the architecture team, collaborating closely with hash core, memory, and compiler groups.

Key Responsibilities

• Develop and maintain cycle-accurate or analytical models of the tile array, NoC, and memory subsystems using C++, SystemC, and Python.
• Conduct workload and roofline analyses to evaluate mapping of tasks onto tile arrays and memory hierarchies.
• Simulate NoC traffic and contention, memory bandwidth, and quality of service under realistic conditions; generate traffic scenarios for architectural evaluation.
• Perform architectural trade-off studies including variables such as tile numbers, local memory capacity, NoC topology and bandwidth, memory channels, and QoS to inform architecture freeze decisions.
• Validate model outputs by correlating predictions against RTL, emulation, FPGA, and silicon data, identifying and addressing discrepancies.
• Provide golden performance reference models and hooks utilized by performance and verification teams during sign-off.
• Maintain performance monitoring dashboards and trade-off summaries for architecture and program leadership to manage performance risks.

Required Qualifications

• Minimum 5 years of experience in performance modeling and architecture for SoCs and accelerators.
• Proficient in C++ and Python with experience in SystemC or equivalent cycle-approximate modeling frameworks.
• Strong understanding of computer architecture fundamentals including memory hierarchies, bandwidth and latency trade-offs, interconnects/NoC behavior, and roofline modeling.
• Proven capability to translate subsystem modeling results into actionable architectural decisions.
• Able to work effectively with partial specifications and collaborate across architecture, design, and software teams.

Preferred Qualifications

• Experience with NoC/interconnect modeling, memory controller functionality, or 3D-DRAM/HBM bandwidth analysis.
• Familiarity with compiler and dataflow co-design for accelerators.
• Track record of correlating performance models with RTL, emulation platforms, or silicon data.
• Background in tile-based or dataflow architectures.

Success Metrics in First 6–12 Months

• Development of a reliable full-chip performance model guiding tile count, NoC, and memory configuration decisions at architecture freeze.
• Establishment of clear, quantified performance targets and a documented plan for correlating models to reality.
• Production of performance trade-off reports trusted by program and architecture leadership.

Work Environment and Culture

• An inclusive culture valuing authenticity and diversity of ideas and backgrounds.
• Open office settings fostering respect and a dynamic start-up atmosphere.
• Opportunity to engage with pioneering industry figures and contribute significantly to the digital asset sector's future.
• Participation in new project initiatives and the development of processes and systems.
• Emphasis on personal responsibility, autonomy, rapid career growth, and continuous learning.
• Competitive welfare benefits and growth opportunities including training and mentoring programs.

Equal Opportunity Statement

Bitdeer is dedicated to equal employment and does not discriminate based on race, color, gender identity and expression, sexual orientation, marital or parental status, religion, political views, nationality, ethnic or social background, social status, disability, age, indigenous origin, or union membership, in accordance with applicable laws.