Static Timing Analysis (STA) Engineer

About the Company

Aryan Solutions is a technology consulting and staffing firm specializing in delivering technology solutions, recruitment, and managed services to leading companies across the Asia-Pacific, Southeast Asia, Australia, and Japan. Their clientele spans financial services, hedge funds, asset management, telecommunications, IT, manufacturing, and public sectors. The company is headquartered in Singapore, with additional offices in USA, Malaysia, and India. They employ experienced consultants operating across Singapore, USA, Malaysia, Indonesia, Hong Kong, China, Australia, and Japan.

Key Responsibilities

• Execute Static Timing Analysis on ASIC/SoC designs at both block and full-chip levels.
• Create, validate, and update SDC timing constraints effectively.
• Identify and address setup, hold, recovery, removal, clock gating, and pulse width timing violations.
• Ensure timing sign-off under diverse PVT (Process, Voltage, Temperature) corners and operating conditions.
• Collaborate with Physical Design teams to achieve timing closure.
• Investigate timing violations and propose RTL or ECO corrections.
• Conduct clock tree analysis and optimize timing performance.
• Review timing reports and provide practical improvement suggestions.
• Assist with ECO deployment and validate timing outcomes.
• Engage in design review sessions and finalize sign-off procedures.

Eligibility & Education

Candidates must have a B.Tech or B.E. degree specializing in Electrical and Electronics Engineering or Electrical Engineering disciplines.