Design Verification Engineer
Hyderabad, Telangana, India · Tempo total
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- Experiência
- 5–7 yrs
- Salário
- —
- Vagas
- 1
- Publicado
- há 3 horas
- Modo de trabalho
- No escritório
- Educação
- Bachelor's degree in Electrical Engineering or Computer Engineering or related field
- Elegibilidade
- Any graduate may apply.
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- Obrigatório candidatar-se
Onde você trabalhará
Descrição da vaga
About the Company
HCL Technologies is a global leader in technology, renowned for innovating over four decades and fostering a culture that values invention and customer focus. With R&D centers worldwide and over 197,000 professionals, they serve top enterprises globally, including many Fortune 500 companies, and promote diversity and sustainability.
Job Overview
We are looking for a driven Design Verification Engineer to join our team and ensure the functionality and quality of next-generation integrated circuits. You will engage in challenging projects utilizing your knowledge of advanced verification methodologies and tools.
Key Responsibilities
- Create and execute detailed verification plans applying recognized industry methods like UVM.
- Develop robust verification environments (testbenches) targeting comprehensive code coverage.
- Use simulation platforms such as ModelSim, Cadence Incisive, or Synopsys VCS to validate RTL designs.
- Investigate and resolve verification errors to pinpoint design faults.
- Work closely with RTL designers to fix functional defects and verify updated designs against requirements.
- Participate in code assessments and maintain coding standard compliance.
- Keep abreast of emerging verification tools and techniques.
Required Qualifications
- Bachelor's degree in Electrical or Computer Engineering or related discipline; Master's degree preferred.
- 5 to 7 years of experience in ASIC or SoC design verification.
- Strong grasp of digital design fundamentals including combinational and sequential logic.
- Experienced in developing and debugging intricate verification environments.
- Skilled in Verilog or VHDL and knowledgeable of methodologies such as UVM.
- Experience with simulation software and scripting languages (Python, Perl) is advantageous.
- Excellent problem-solving abilities along with strong communication and teamwork skills.
Benefits
- Attractive remuneration and benefits package.
- Opportunity to engage with cutting-edge technologies and projects.
- Supportive, collaborative, and dynamic workplace culture.
- Pathways for professional growth and advancement.