STA Engineer

Role Overview

We are seeking an STA Engineer to collaborate intimately with design teams to grasp design requirements and limitations effectively. The role involves developing and implementing constraints at both block and top levels to facilitate synthesis and static timing analysis (STA).

Key Responsibilities

• Collaborate with design teams to thoroughly understand design requirements and constraints.
• Create and enforce block-level and top-level constraints for synthesis and STA processes.
• Conduct static timing analysis preferably utilizing both Tempus and PrimeTime tools.
• Perform STA and achieve timing closure with MMMC in both functional and DFT (Design for Test) modes.
• Generate and validate Synopsys Design Format (SDF) files and provide support to the functional verification team during gate-level simulation (GLS).
• Generate and validate ETM (Embedded Test Model) or timing models at the IP level.
• Partner with SoC teams to provide IP-level support within the SoC integration.