RTL Design Engineer

Position Overview

We are looking for an experienced RTL Design Engineer with a background of 5 to 11 years in ASIC/SoC design to lead the creation of high-performance digital designs from initial architecture through to implementation.

Key Responsibilities and Skills

• Design RTL code primarily using Verilog/SystemVerilog or VHDL.
• Engage actively in ASIC and SoC development processes.
• Apply strong knowledge of digital design fundamentals covering combinational and sequential logic as well as finite state machines (FSMs).
• Conduct functional verification and resolve RTL-level issues through debugging.
• Utilize expertise in timing analysis, achieving timing closure, and working with SDC constraints.
• Collaborate effectively with teams involved in Design, Verification, and Synthesis throughout the development lifecycle.

Preferred Additional Skills

• Experience working with UVM-based verification environments.
• Proficiency in scripting languages like Python, Perl, or Shell.
• Knowledge of static timing analysis (STA) and synthesis flow procedures.

Educational Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a closely related discipline.

Why Join Our Team?

• Work on advanced ASIC/SoC technological projects.
• Thrive in a cooperative, dynamic engineering atmosphere.
• Access substantial opportunities for learning and professional development.
• Enjoy a competitive salary and comprehensive benefits package.