ASIC Verification Engineer - PCIe

Position Summary

We are looking for a seasoned PCIe Verification Engineer to join our silicon engineering team in Bangalore. The role involves leading pre-silicon verification of advanced ASICs with PCIe Gen6 and Gen7 protocols, ensuring robust design validation through comprehensive verification methodologies.

Key Responsibilities

• Design, implement, and sustain sophisticated constrained-random verification environments from the ground up utilizing SystemVerilog and UVM frameworks.
• Develop detailed verification plans, elaborate test scenarios, and functional coverage models aligned with PCIe Gen6/Gen7 architectural specifications.
• Perform verification across block-level, subsystem, and full-chip SoC to guarantee protocol compliance and full functionality.
• Collaborate with RTL designers to debug complex hardware designs, testbench components, and resolve protocol violations.
• Integrate third-party PCIe verification IPs ensuring correct configuration for high-speed link training, physical layer operations, and data routing.
• Lead efforts to meet and surpass functional and code coverage objectives to achieve complete verification closure.
• Provide mentorship to junior engineers and coordinate with global design and verification teams to expedite product delivery.

Qualifications and Technical Expertise

• B.E./B.Tech/M.E./M.Tech degree in Electronics, Electrical, Computer Engineering, or equivalent disciplines.
• 7 to 8+ years of practical experience in ASIC/SoC pre-silicon verification, with a significant focus on PCIe protocols.
• In-depth understanding of PCIe Gen6 and/or Gen7 architecture including flit-based structures, PAM4 signaling at the protocol level, reliability and serviceability (RAS) features, virtualization capabilities, and low-power state management.
• Expertise in SystemVerilog and Universal Verification Methodology (UVM) techniques.
• Hands-on experience developing UVM testbenches, implementing SVA assertions, functional coverage models, and designing test cases.
• Familiarity with major EDA verification tools such as Synopsys VCS, Cadence Xcelium, or Siemens/Mentor Graphics Questa.
• Proficient in scripting languages like Python, Perl, or Shell for automating verification tasks.

Additional Information

• Work Location: Bangalore, India
• Notice Period: Immediate to 30 days preferred
• Open to candidates with any graduate degree