RTL Design Engineer - SMTS

About the Company

Tsavorite Scalable Intelligence is building a new semiconductor computing platform centered on the first Omni Processing Unit (OPU), a composable architecture aimed at powering real-time, multimodal Agentic AI. Established in 2023 by leaders with experience at Intel, Nvidia, Qualcomm, and Apple, the company is focused on removing the cost, power, and complexity limits of older GPU-based systems. Its platform is positioned to deliver around 10x better performance at roughly 10% of the energy use, with scale that spans from edge devices to exascale data centers.

Why Engineers Choose This Team

• Architectural innovation: contribute to the MultiPlexus™ fabric, an advanced interconnect designed for petabyte-scale bandwidth and very low latency.
• End-to-end product influence: work across modular chiplets built on Samsung’s SF4X platform and the Tsavorite AI Orchestration Stack (TAOS), which supports CUDA-optimized workflows with no switching cost.
• Strong market traction: the company has come out of stealth with more than $100 million in pre-orders from Global 500 organizations and sovereign cloud providers.

Role Summary

This position sits at the boundary between architecture and implementation. As a front-end RTL Design Engineer, you will convert system-level ideas into efficient, production-ready RTL for key SoC subsystems and IP blocks. The role calls for someone who can solve complex design problems while preserving design quality through synthesis, timing analysis, and verification.

Core Responsibilities

• Turn architectural intent into clear and detailed micro-architecture specifications.
• Create high-quality, synthesizable RTL in Verilog and SystemVerilog with a focus on performance, power, and area goals.
• Evaluate implementation alternatives and make informed trade-offs among latency, throughput, and silicon usage.
• Own the front-end ASIC flow, including synthesis, clock-domain crossing, and reset-domain crossing work.
• Drive timing closure so the design meets target frequencies across process, voltage, and temperature corners.
• Work closely with verification and physical design partners to refine and iterate on implementations.
• Investigate and resolve issues found in simulation, lint, CDC, RDC, and synthesis stages.

Required Background

• Bachelor’s or Master’s degree in EC, EE, CS, or a related discipline.
• 8 to 14+ years of experience in SoC or subsystem-level design.
• Strong working knowledge of AMBA protocols, especially CHI, AXI, AHB, and APB.
• Advanced hands-on expertise in Verilog, SystemVerilog, and micro-architecture development.
• Practical experience with CDC/RDC analysis tools, lint tools, and logic synthesis tools such as Design Compiler or Genus.
• Solid command of static timing analysis and timing-constraint development.
• Familiarity with ARM architecture is an added advantage.
• Ability to communicate technical trade-offs clearly to different stakeholders.

Additional Information

This role is based in Greater Bengaluru Area and is a full-time, onsite position. The source also references external company and news links, which have been omitted here. A closing tagline appears in the source: “Mining the Knowledge Community.”