Staff RISC-V CPU Design Engineer

Role overview

An opportunity is available for a Staff-level RISC-V CPU Design Engineer to contribute to advanced CPU RTL work for high-performance, low-power products. The position involves close collaboration with chip architects and other engineering specialists to help define and evolve CPU microarchitecture using the RISC-V ISA.

The role is based in Cork, County Cork, Ireland, a well-connected technology location known for its innovation ecosystem and quality of life.

Key responsibilities

• Work with the CPU modeling team to investigate approaches that improve performance.
• Take part in early-stage architectural studies, microarchitecture research, and the creation of detailed technical specifications.
• Own RTL development tasks and continuously improve designs to achieve targets for power, performance, area, and timing.
• Support the verification team with functional validation activities.
• Help confirm that the RTL implementation meets performance goals.
• Partner with cross-functional engineers to deliver and validate physical design, with attention to timing, area, reliability, and testability.

Required qualifications

The role calls for a bachelor’s degree in Computer Science, Electrical/Electronics Engineering, or a similar discipline, together with at least 4 years of relevant experience.

Candidates should have strong knowledge of microprocessor architecture and practical familiarity with one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution, integer and floating-point execution, load/store design, prefetching, caches, and memory subsystems.

Hands-on experience with Verilog and/or VHDL is required, along with the ability to use simulation tools and waveform debugging tools effectively.

A solid grasp of logic design fundamentals, especially the impact of timing and power, is important. Experience with low-power CPU techniques, high-performance microarchitecture trade-offs, and scripting in Perl or Python will also be valuable.

Additional information

This is a full-time onsite position. The role is intended for a senior engineer who can contribute at staff level and work across design, verification, and implementation teams.

Interested candidates are asked to share their CV and suggest a suitable time for a call.

Who this role suits

This opportunity is suited to experienced CPU design professionals who want to work on RISC-V processor development, enjoy deep architectural problem-solving, and can contribute across the RTL, verification, and physical design lifecycle.

Note

No salary, vacancy count, start date, or application deadline was specified in the source information.